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_______________general description the max1624/max1625 are ultra-high-performance, step-down dc-dc controllers for cpu power in high-end computer systems. designed for demanding applications in which output voltage precision and good transient response are critical for proper operation, they deliver over 35a from 1.1v to 3.5v with ?% total accuracy from a +5v ?0% supply. excellent dynamic response cor- rects output transients caused by the latest dynamically clocked cpus. these controllers achieve over 90% effi- ciency by using synchronous rectification. flying-capaci- tor bootstrap circuitry drives inexpensive, external n-channel mosfets. the switching frequency is resistor programmable from 100khz to 1mhz. high switching frequencies allow the use of a small surface-mount inductor and decrease out- put filter capacitor requirements, reducing board area and system cost. the max1624 is available in a 24-pin ssop and offers additional features such as a digitally programmable out- put in 100mv increments; adjustable transient response; selectable 0.5%, 1%, or 2% ac load regulation; and gate drive for a current-boost mosfet. the max1625 is resis- tor adjustable and comes in a 16-pin narrow so pack- age. other features in both controllers include internal digital soft-start, a power-good output, and a 3.5v ?% reference output. for a similar controller compatible with the latest intel v rm /v id specification, see the max1638* data sheet. ________________________applications pentium pro, pentium ii, powerpc, alpha, and k6 systems desktop computers lan servers industrial computers gtl bus termination ____________________________features ? better than ?% output accuracy over line and load ? 90% efficiency ? excellent transient response ? resistor-programmable fixed switching frequency from 100khz to 1mhz ? over 35a output current ? digitally programmable output from 1.1v to 3.5v in 100mv increments (max1624) ? resistor-adjustable output down to 1.1v (max1625) ? remote sensing ? adjustable ac loop gain (max1624) ? glitchcatcher circuit for fast load-transient response (max1624) ? power-good (pwrok) output ? current-mode feedback ? digital soft-start ? strong 2a gate drivers ? current-limited output max1624/max1625 high-speed step-down controllers with synchronous rectification for cpu power ________________________________________________________________ maxim integrated products 1 19-1227; rev 1; 6/97 part max1624 eag max1625 ese -40? to +85? -40? to +85? temp. range pin-package 24 ssop 16 narrow so ______________ordering information __________typical operating circuit pin configurations appear at end of data sheet. * future product. pentium pro and pentium ii are trademarks of intel corp. powerpc is a trademark of ibm corp. alpha is a trademark of digital equipment corp. k6 is a trademark of advanced micro devices. glitchcatcher is a trademark of maxim integrated products. evaluation kit available v cc freq cc2 cc1 ref agnd (simplified) fb dl dh pwrok bst csl csh lx to v dd to agnd pgnd output 1.1v to 4.5v input +5v v dd n n max1625 for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468.
khz max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = v cc = d4 = +5v, pgnd = agnd = d0?3 = 0v, r freq = 33.3k , t a = 0 c to +85 c , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , v cc , pwrok to agnd ...................................... -0.3v to 6v pgnd to agnd .................................................................. 0.3v csh, csl to agnd .................................... -0.3v to (v cc + 0.3v) ndrv, pdrv, dl to pgnd ......................... -0.3v to (v dd + 0.3v) ref, cc1, cc2, lg, d0?4, freq, fb to agnd ................................................ -0.3v to (v cc + 0.3v) bst to pgnd ............................................................ -0.3v to 12v bst to lx .................................................................... -0.3v to 6v dh to lx ............................................. (lx - 0.3v) to (bst + 0.3v) continuous power dissipation (t a = 70 c) 24 pin ssop (derate 8.00mw/ c above +70 c) .......... 640mw 16 pin narrow so (derate 8.70mw/ c above 70 c) ..... 696mw operating temperature range max162_e_ _ ....................................................... -40 c to +85 c storage temperature range ............................. -65 c to +125 c lead temperature (soldering, 10sec) ............................. +300 c r freq = 33.3k r freq = 20k pwrok = 5.5v v cc = v dd = 5.5v, fb overdrive = 200mv i sink = 2ma, v cc = 4.5v falling fb, 1% hysteresis with respect to v ref v cc rising edge, 1% hysteresis rising fb, 1% hysteresis with respect to v ref v cc = v dd max1624, over line and load (note 1) v ref = 0v rising edge, 1% hysteresis 0 a < i load < 100 a v cc = v dd = 5.5v, fb overdrive = 200mv, operating or standby mode max1625, over line and load (note 2) no load conditions 540 600 660 850 1000 1150 switching frequency a 1 pwrok output current high v 0.4 pwrok output voltage low 6.5 8 9.5 % -7.5 -6 -4.5 pwrok trip level 1 2 1 % 0.5 ac load regulation (note 3) 1.5 % 1 fb set voltage 1.5 2.5 v cc supply current v 4.0 4.2 v 4.5 5.5 input voltage range input undervoltage lockout % 1 fb accuracy ma 0.5 4.0 reference short-circuit current v 2.7 3.0 reference undervoltage lockout mv 10 reference load regulation ma 0.3 ma 0.1 v dd supply current v 3.465 3.5 3.535 reference voltage units min typ max parameter operating mode standby mode t a = +25 c to +85 c t a = 0 c to +85 c t a = +25 c to +85 c t a = 0 c to +85 c csh - csl = 0mv to 80mv r freq = 200k khz 85 100 115 lg = ref lg = gnd lg = v cc max1624 max1625 lg = ref csh - csl = 0mv to 80mv lg = gnd lg = v cc 0.1 max1624 max1625 0.2 0.1 % 0.05 dc load regulation (note 3)
electrical characteristics (continued) (v dd = v cc = d4 = +5v, pgnd = agnd = d0?3 = 0v, r freq = 33.3k , t a = 0 c to +85 c , unless otherwise noted.) max1624/max1625 _______________________________________________________________________________________ 3 dh = dl = 2.5v v dd = 4.5v bst - lx = 4.5v lg = gnd (low) 100mv overdrive r freq = 20k with respect to v ref , fb going low minimum max1625, csh = csl = 1.1v d0?4 = 0v, 5v d0?4; v cc = 4.5v lg = ref (mid) max1624, csh = csl = 1.3v, d0?3 = 5v, d4 = 0v d0?4; v cc = 5.5v conditions -2.75 -2 -1.25 lg = v cc (high) ns 0 30 fb = 1.1v dh, dl dead time a 2 dh, dl source/sink current 0.7 2 maximum dh on-resistance 0.7 2 % -3 -1 a 100 cc2 source/sink current 4 v cc v 2.4 3.0 mmho 1 k 10 cc1 output resistance a 0.1 50 3.3 3.7 0.2 % 85 90 maximum duty cycle lg input voltage a 50 csh, csl input current a 4 lg input current a 1 d0?4 input current v 2.0 logic input voltage high v cc - 0.2 v 0.8 logic input voltage low units min typ max parameter fb input current cc2 clamp voltage cc2 transconductance pdrv trip level pdrv, ndrv response time fb overdrive = 5% ns 75 pdrv, ndrv on-resistance v dd = 4.5v 2 5 pdrv, ndrv source/sink current pdrv = ndrv = 2.5v a 0.5 pdrv, ndrv minimum on-time ns 100 current-limit trip voltage mv 85 100 115 soft-start time to full current limit 1 / f osc 1536 bst leakage current bst = 12v, lx = 7v, ref = gnd a 50 v high-speed step-down contr ollers with synchr onous rectification for cpu power dl on-resistance ndrv trip level with respect to v ref , fb going high 1.25 2 2.75 % 1 3 t a = +25 c t a = 0 c to +85 c t a = +25 c t a = 0 c to +85 c
ma max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 4 _______________________________________________________________________________________ r freq = 33.3k r freq = 20k v cc = v dd = 5.5v, fb overdrive = 200mv falling fb, 1% hysteresis with respect to v ref v cc rising edge, 1% hysteresis rising fb, 1% hysteresis with respect to v ref v cc = v dd r freq = 200k operating mode v cc = v dd = 5.5v, fb overdrive = 200mv, operating or standby mode max1624, over line and load no load conditions 510 600 690 standby mode 800 1000 1200 switching frequency 6 8 10 khz 80 100 120 % -8 -6 -4 pwrok trip level 2.5 3 v cc supply current v 3.9 4.3 v 4.5 5.5 input voltage range input undervoltage lockout % 2.5 fb accuracy ma 0.4 ma 0.2 v dd supply current v 3.447 3.5 3.553 reference voltage units min typ max parameter max1625 fb set voltage bst - lx = 4.5v r freq = 20k v dd = 4.5v 0.7 2 % 84 90 0.7 2 maximum duty cycle dl on-resistance dh on-resistance current-limit trip voltage mv 70 100 130 electrical characteristics (v dd = v cc = d4 = +5v, pgnd = agnd = d0?3= 0v, r freq = 33.3k , t a = -40 c to +85 c , unless otherwise noted.) (note 4) note 1: fb accuracy is 100% tested at fb = 3.5v (code 10000) with v cc = v dd = 4.5v to 5.5v and csh - csl = 0mv to 80mv. the other dac codes are tested at the major transition points with v cc = v dd = 5v and csh - csl = 0. fb accuracy at other dac codes over line and load is guaranteed by design. note 2: fb set voltage is 100% tested with v cc = v dd = 4.5v to 5.5v and csh - csl = 0mv to 80mv. note 3: ac load regulation sets the ac loop gain, to make tradeoffs between output filter capacitor size and transient response, and has only a slight effect on dc accuracy or dc load-regulation error. note 4: specifications from 0 c to -40 c are not production tested. %
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power _______________________________________________________________________________________ 5 __________________________________________ t ypical operating characteristics (t a = +25 c, using the max1624 evaluation kit, unless otherwise noted.) 10 m s/div max1624 load-transient response detail (with glitchcatcher) (1.1v) c d max1624/25 toc01 a: pdrv, 5v/div b: v out , 50mv/div, ac coupled c: ndrv, 5v/div d: load current, 0a to 10a, t rise = t fall = 100ns b a lg = ref 10 m s/div max1624 load-transient response (with glitchcatcher) (1.1v ) c max1624/25 toc02 a: v out , 50mv/div, ac coupled b: inductor current, 10a/div c: load current, 0a to 10a, t rise = t fall = 100ns b a lg = ref 10 m s/div max1624 load-transient response (without glitchcatcher) (1.1v) c max1624/25 toc03 a: v out , 50mv/div, ac coupled b: inductor current, 10a/div c: load current, 0a to 10a, t rise = t fall = 100ns b a lg = ref 10 m s/div max1624 load-transient response (without glitchcatcher) (3.5v) c max1624/25 toc15 a: v out , 100mv/div, ac coupled b: inductor current, 10a/div c: load current, 0a to 11a, t rise = t fall = 100ns b a lg = ref 10 m s/div max1624 load-transient response (with glitchcatcher) (2.5v) c max1624/25 toc17 a: v out , 50mv/div, ac coupled b: inductor current, 10a/div c: load current, 0a to 10a, t rise = t fall = 100ns b a lg = ref 10 m s/div max1624 load-transient response (without glitchcatcher) (2.5v) c max1624/25 toc18 a: v out , 50mv/div, ac coupled b: inductor current, 10a/div c: load current, 0a to 10a, t rise = t fall = 100ns b a lg = ref
10 m s/div max1624 load-transient response (with glitchcatcher) (3.5v) c max1624/25 toc16 a: v out , 100mv/div, ac coupled b: inductor current, 10a/div c: load current, 0a to 11a, t rise = t fall = 100ns b a lg = ref 1 m s/div max1624 switching waveforms c 0 max1624/25 toc10 v in = 5v, v out = 2.5v, load = 5a a: lx, 5v/div b: v out , 20mv/div, ac coupled c: inductor current, 5a/div b a 1ms/div max1624 startup and standby response c max1624/25 toc11 v in = 5v, v out = 2.5v, load = 13.8a a: v out , 1v/div b: inductor current, 10a/div c: standby, d0?4 b a max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 6 _______________________________________________________________________________________ ____________________________ t ypical operating characteristics (continued) (t a = +25 c, using the max1624 evaluation kit, unless otherwise noted.) 100 0 0.1 1 10 max1624 efficiency vs. output current (v out = 1.1v) 20 10 max1624/25 toc04 output current (a) efficiency (%) 40 30 60 70 50 80 90 100 0 0.1 1 10 max1624 efficiency vs. output current (v out = 2.5v) 20 10 max1624/25 toc05 output current (a) efficiency (%) 40 30 60 70 50 80 90 100 0 0.1 1 10 max1624 efficiency vs. output current (v out = 3.5v) 20 10 max1624/25 toc06 output current (a) efficiency (%) 40 30 60 70 50 80 90
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power _______________________________________________________________________________________ 7 ____________________________ t ypical operating characteristics (continued) (t a = +25 c, using the max1624 evaluation kit, unless otherwise noted.) 1.1020 1.1000 0.1 1 0.01 10 max1624 output voltage vs. output current (v out = 1.1v) 1.1002 1.1006 1.1004 max1624/25 toc07 output current (a) output voltage (v) 1.1008 1.1010 1.1014 1.1012 1.1016 1.1018 lg = v cc lg = ref lg = agnd r9 and r10 = 4.7 w 2.500 2.490 0.1 1 0.01 10 max1624 output voltage vs. output current (v out = 2.5v) 2.491 2.492 max1624/25 toc08 output current (a) output voltage (v) 2.493 2.494 2.496 2.495 2.497 2.498 2.499 lg = v cc lg = ref lg = agnd r9 and r10 = 4.7 w 3.500 3.480 0.1 1 0.01 10 max1624 output voltage vs. output current (v out = 3.5v) 3.482 3.486 3.484 max1624/25 toc09 output current (a) output voltage (v) 3.488 3.494 3.490 3.492 3.496 3.498 lg = v cc lg = ref lg = agnd r9 and r10 = 4.7 w 5.094 1.094 0.001 0.1 1 0.01 10 reference voltage vs. output current 1.594 2.094 max1624/25 toc12 output current (ma) reference voltage (v) 2.594 3.594 3.094 4.094 4.594 sourcing current sinking current 50 55 0 maximum duty cycle vs. switching frequency 65 60 70 max1624/25 ttoc13 switching frequency (khz) maximum duty cycle (%) 85 95 90 75 80 200 800 1000 1200 100 600 400 10 -10 1.7 2.3 2.9 1.1 3.5 max1624 output error vs. dac output voltage setting -8 -4 -6 max1624/25 toc19 dac output voltage setting (v) output error (mv) -2 4 0 2 6 8
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 8 _______________________________________________________________________________________ max1625 max1624 pin high-side main mosfet switch gate-drive output. dh is a floating driver output that swings from lx to bst, riding on the lx switching-node voltage. see the section bst high-side gate-driver supply and mosfet drivers . dh 16 24 switching node. connect lx to the high-side mosfet source and inductor. lx 15 23 power ground pgnd 14 22 dl low-side synchronous rectifier gate-drive output. dl swings between pgnd and v dd . see the section bst high-side gate-driver supply and mosfet drivers . 13 21 v dd 5v power input for mosfet drivers. bypass v dd to pgnd within 0.2 in. (5mm) of the v dd pin using a 0.1 f capacitor and 4.7 f capacitor connected in parallel. 12 20 pdrv glitchcatcher p-channel mosfet driver output. pdrv swings between v dd and pgnd. 19 ndrv glitchcatcher n-channel mosfet driver output. ndrv swings between v dd and pgnd. 18 d4, d3 digital inputs for programming the output voltage 16, 17 freq frequency-programming input. attach a resistor within 0.2 in. (5mm) of freq to agnd to set the switching frequency between 100khz and 1mhz. the freq pin is normally 2v dc. 11 15 cc2 slow-loop compensation capacitor input. connect a ceramic capacitor from cc2 to agnd. see the section compensating the feedback loop. 10 14 bst boost-capacitor bypass for high-side mosfet gate drive. connect a 0.1 f capacitor and low-leakage schottky diode as a bootstrapped charge-pump circuit to derive a 5v gate drive from v dd for dh. 1 1 name function ______________________________________________________________ pin description cc1 fast-loop compensation capacitor input. connect a ceramic capacitor and resistor in series from cc1 to agnd. see the section compensating the feedback loop . 9 13 fb voltage-feedback input. max1624: connect fb to the cpu? remote voltage-sense point. the voltage at this input is regulated to a value determined by d0?4. max1625: connect a feedback resistor voltage divider close to fb from the output to agnd. fb is regulated to 1.1v. 8 12 pwrok open-drain logic output. pwrok is high when the voltage on fb is within +8% and -6% of its setpoint. 2 2 csl current-sense amplifier? inverting input. place the current-sense resistor very close to the controller ic, and use a kelvin connection. use an rc filter network at csl (figure 1). 3 3 csh current-sense amplifier? noninverting input. use an rc filter network at csh (figure 1). 4 4 d2, d1, d0 digital inputs for programming the output voltage. d0?4 are logic inputs that set the output to a voltage between 1.1v and 3.5v in 100mv increments. 5, 6, 7 lg loop gain-control input. lg is a three-level input that is used to trade off loop gain vs. ac load-regulation and load-transient response. connect lg to v cc , ref, or agnd for 2%, 1%, or 0.5% ac load-regulation errors, respectively. 8 v cc analog supply input, 5v. use an rc filter network, as shown in figure 1. 5 9 ref reference output, 3.5v. bypass ref to agnd with 0.1 f (min). sources up to 100 a for external loads. force ref below 2v to turn off the controller. 6 10 agnd analog ground 7 11
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power _______________________________________________________________________________________ 9 n1 r1 n2 c2 d1 (optional) r9 (optional) r10 (optional) r8 39 w c12 4.7nf c11 4.7nf v cc v dd csh pwrok csl bst dh lx dl pgnd fb pdrv ndrv agnd ref cc1 cc2 cc2 cc1 rc1 to agnd c6, 1.0 m f ceramic r4, 40.1k for 500khz r5 100k c9 0.1 m f c7 4.7 m f r6 100 w to v dd freq d0 d1 d2 d3 d4 lg ref c5 0.1 m f c8 4.7 m f d2 cmpsh-3 c4 0.1 m f l1 v in = 5v c1 r7 39 w local bypassing max1624 p1 r11 v out = 1.1v to 3.5v n3 load figure 1. max1624 standard application circuit
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 10 ______________________________________________________________________________________ local bypassing n1 r1 n2 c2 r3 100k w r2 200k w c10 (optional) d1 (optional) r9 (optional) r10 (optional) c12 4.7nf c11 4.7nf v cc v dd csh pwrok csl bst dh lx dl pgnd fb agnd ref cc1 cc2 cc2 cc1 rc1 to agnd c6, 1.0 m f ceramic r4, 40.1k w for 500khz r5 100k w c9 0.1 m f c7 4.7 m f r6 100 w to v dd freq c5 0.1 m f c8 4.7 m f d2 cmpsh-3 c4 0.1 m f v in = 5v c1 r7 39 w r8 39 w load v out l1 max1625 figure 2. max1625 standard application circuit
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power ______________________________________________________________________________________ 11 table 1. component list for standard 3.3v applications by load current* (output voltage = 3.3v, frequency = 500khz) * max1624: lg = ref, d4?0 = 10010. c10 capacitor cc1 capacitor d2 rectifier l1 inductor r2 resistor r3 resistor application equipment r11 resistor (max1624) c1 input capacitor 100 f, 10v sanyo os-con 10sl100m optional (see text) 680pf ceramic 1.5 h, 8a coiltronics up2-1r5 200k , 1% resistor 100k , 1% resistor power pc/pentium/gtl bus termination 3 x 100 f, 10v sanyo os-con 10sl100m 1000pf ceramic 0.5 h, 17a coilcraft do5022p-501hc n/a n/a pentium pro 500m dale wsl-2512-r500 c2 output capacitor 2 x 220 f, 4v sanyo os-con 4sp220m 3 x 220 f, 4v sanyo os-con 4sp220m 0.056 f ceramic 0.056 f ceramic cc2 capacitor optional schottky, nihon nsq03a02 optional schottky, nihon nsq03a02 d1 rectifier 1k , 5% resistor 1k , 5% resistor rc1 resistor international rectifier irf7413 international rectifier irl3103s, d 2 pak n1 high-side mosfet international rectifier irf7413 international rectifier irl3103s, d 2 pak international rectifier irf7107 n3/p1 (max1624) n2 low-side mosfet 12m dale wsl-2512-r012-f 2 x 12m in parallel, dale wsl-2512-r012-f r1 resistor 6a 12a component 3 x 2700 f, 6.3v aluminum electrolytic, sanyo 6mv2700gx 1000pf ceramic central semiconductor cmpsh-3 0.5 h coiltronics up4-r47, coilcraft do5022p-501hc n/a n/a pentium pro n/a description by load current 4 x 2700 f, 6.3v aluminum electrolytic, sanyo 6mv2700gx 0.056 f ceramic optional schottky, nihon nsq03a02 11a (low-cost v rm ) 1k , 5% resistor international rectifier irf7413 x 2 international rectifier irf7413 x 2 2 x 12m in parallel dale wsl-2512-r012-f central semiconductor cmpsh-3 central semiconductor cmpsh-3
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 12 ______________________________________________________________________________________ avx (803) 946-0690 (803) 626-3123 coilcraft (847) 639-6400 (847) 639-1469 dale inductors (605) 668-4131 (605) 665-1627 coiltronics (561) 241-7876 (561) 241-9339 international rectifier (310) 322-3331 (310) 322-3332 central semiconductor (516) 435-1110 (516) 435-1824 irc (512) 992-7900 (512) 992-3377 matsuo (714) 969-2491 (714) 960-6492 motorola (602) 303-5454 (602) 994-6430 murata-erie (814) 237-1431 (814) 238-0490 nichicon (847) 843-7500 (847) 843-2798 niec (805) 867-2555* [81] 3-3494-7414 sanyo (619) 661-6835 [81] 7-2070-1174 siliconix (408) 988-8000 (408) 970-3950 supplier usa phone factory fax sprague (603) 224-1961 (603) 224-1430 sumida (847) 956-0666 [81] 3-3607-5144 * distributor ? see table 4 for a complete listing. d4 d2 d0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 1 1 d3 0 1 1 0 0 0 0 0 1 1 1 1 d1 0 1 1 0 0 0 1 0 1 1 output voltage (v) 3.4 2.1 decreases in 100mv incre ments no cpu (off) 3.5 1.9 1.8 decreases in 100mv increments 1.2 1.1 1.1 1.1 no cpu (off) compatibility intel-compatible codes non-intel compatible codes table 2. component suppliers table 3. max1624 output voltage adjustment settings (abbreviated ? ) _____ standar d application cir cuits the predesigned max1624/max1625 circuits shown in figures 1 and 2 meet a wide range of applications with output currents up to 12a and higher. use table 1 to select components appropriate for the desired output current range, and adapt the evaluation kit pc board layout as necessary. table 2 lists suggested vendors. these circuits represent a good set of trade-offs between cost, size, and efficiency while staying within the worst-case specification limits for stress-related parameters, such as capacitor ripple current. these max1624/max1625 circuits were designed for the specified frequencies. do not change the switching frequency without first recalculating component val - ues?articularly the inductance, output filter capaci - tance, and rc1 resistance values. recalculate the voltage-feedback resistor and compensation-capacitor values (cc1 and cc2) as necessary to reconfigure them for different output voltages. table 3 lists voltage adjustment dac codes for the max1624. _______________ detailed description the max1624/max1625 are bicmos switch-mode, power-supply controllers designed for buck-topology regulators. they are optimized for powering the latest high-performance cpus?emanding applications where output voltage precision, good transient response, and high efficiency are critical for proper operation. with appropriate external components, the max1624/max1625 deliver over 15a between 1.1v and 3.5v with 1% accuracy. the max1625 offers 1% typi - cal transient-load regulation from a +5v supply, while the max1624 offers a selectable transient-load regulation of 0.5%, 1%, or 2%. remote output sensing ensures volt - age precision by eliminating errors caused by pc board trace impedance. these controllers achieve 90% effi - ciency by using synchronous rectification. a typical application circuit consists of two n-channel mosfets, a rectifier, and an lc output filter (figure 1). at each of the internal oscillator? rising edges, the high-side mosfet switch (n1) is turned on and allows current to ramp up through the inductor to the output filter capacitor and load, storing energy in a magnetic field. the current is monitored by reading the voltage
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power ______________________________________________________________________________________ 13 across the current-sense resistor (r1). when the induc - tor current ramps up to the current-sense threshold, the mosfet turns off and interrupts the flow of current from the supply. this causes the magnetic field in the induc - tor to collapse, resulting in a voltage surge that forces the rectifier diode (d1) or mosfet body diode (n2) on and keeps the inductor current flowing in the same amplitude and direction. at this point, the synchronous rectifier mosfet turns on until the end of the cycle to reduce conduction losses across the rectifier diode. the current through the inductor ramps back down, transferring the stored energy to the output filter capac - itor and load. the output filter capacitor stores energy when inductor current is high and releases it when inductor current is low, smoothing the voltage delivered to the load. the max1624/max1625 use a current-mode pulse- width-modulation (pwm) control scheme (figures 3 and 4). the output voltage is regulated by switching at a constant frequency and then modulating the peak inductor current to change the energy transferred per pulse and to adjust to changes in the load. the output + - + - ref ref4 agnd ref3 ref2 ref fb d0?4 pwrok pdrv ndrv cc2 cc1 ref1 5 n 10k 40k window control and drive logic oscilla tor slope compensa tion ref agnd v cc freq ref ref1 ref2 ref3 ref4 csl csh lg bst dh lx v dd dl reset q q set pgnd max1624 figure 3. max1624 simplified block diagram
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 14 ______________________________________________________________________________________ voltage is the average of the ac voltage at the switching node, which is adjusted and regulated by changing the duty cycle of the mosfet switches. slope compensa - tion is necessary to stabilize current-mode feedback controllers with a duty cycle greater than 50%. maximum duty cycle is greater than 85% (see typical operating characteristics ). pwm controller block and integrator the heart of the current-mode pwm controller is a multi-input open-loop comparator that sums three sig - nals: the buffered feedback signal, the current-sense signal, and the slope-compensation ramp. this direct- summing configuration approaches ideal cycle-by- cycle control over the output voltage. the output voltage error signal is generated by an error amplifier that compares the amplified feedback voltage to an internal reference. each pulse from the oscillator sets the main pwm latch that turns on the high-side switch for a period deter - mined by the duty factor (approximately v out / v in ). the current-mode feedback system regulates the peak inductor current as a function of the output voltage ref ref2 n fb ref cc2 cc1 pwrok ref1 10k 40k window control and drive logic oscilla tor slope compensa tion ref agnd v cc freq ref ref1 ref2 csl csh bst dh lx v dd reset q q set dl pgnd max1625 figure 4. max1625 simplified block diagram
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power ______________________________________________________________________________________ 15 error signal. since average inductor current is nearly the same as peak current (assuming the inductor value is set relatively high to minimize ripple current), the cir - cuit acts as a switch-mode transconductance amplifier. it pushes the second output lc filter pole, normally found in a duty-factor-controlled (voltage-mode) pwm, to a higher frequency. to preserve inner-loop stability and eliminate regenerative inductor current staircasing, a slope-compensation ramp is summed into the main pwm comparator. as the high-side switch turns off, the synchronous rectifier latch is set. the low-side switch turns on 30ns later and stays on until the beginning of the next clock cycle. under fault conditions where the inductor current exceeds the maximum current-limit threshold, the high-side latch resets, and the high-side switch turns off. internal reference the internal 3.5v reference (ref) is accurate to 1% from 0 c to +85 c, making ref useful as a system ref - erence. bypass ref to agnd with a 0.1 f (min) ceramic capacitor. a larger value (such as 1 f) is rec - ommended for high-current applications. load regula - tion is 10mv for loads up to 100 a. loading ref reduces the main output voltage slightly, according to the reference-voltage load-regulation error (see typical operating characteristics ). reference undervoltage lockout is between 2.7v and 3v. short-circuit current is less than 4ma. synchronous-rectifier driver synchronous rectification reduces conduction losses in the rectifier by shunting the normal schottky diode or mosfet body diode with a low-on-resistance mosfet switch. the synchronous rectifier also ensures proper start-up by precharging the boost-charge pump used for the high-side switch gate-drive circuit. thus, if you must omit the synchronous power mosfet for cost or other reasons, replace it with a small-signal mosfet, such as a 2n7002. the dl drive waveform is simply the complement of the dh high-side drive waveform (with typical controlled dead time of 30ns to prevent cross-conduction or shoot-through). the dl output? on-resistance is 0.7 (typ) and 2 (max). bst high-side gate-driver supply and mosfet drivers gate-drive voltage for the high-side n-channel switch is generated using a flying-capacitor boost circuit (fig- ure 5). the capacitor is alternately charged from the +5v supply and placed in parallel with the high-side mosfet? gate and source terminals. on start-up, the synchronous rectifier (low-side mosfet) forces lx to 0v and precharges the bst capacitor (c4) to 5v through a diode (d2). this pro - vides the necessary enhancement voltage to turn on the high-side switch. on the next half-cycle, the pwm control logic turns on the high-side mosfet by closing an internal switch between bst and dh. as the mos - fet turns on, the lx node rises to the input voltage, an action that boosts the 5v gate-drive signal above the +5v supply. dh on-resistance is 0.7 (typical) and 2 (max). do not bias d2 with voltages greater than 5.5v, as this will destroy the dh gate driver. a 0.1 f minimum ceramic capacitor is recommended for the boost supply. use a low-power, sot23 schottky diode to minimize reduction of the gate drive from the diode? forward voltage. use a low-leakage schottky diode, such as a cmpsh-3 from central semiconductor or a 1n4148, to prevent reverse leakage from discharg - ing the bst capacitor when the ambient temperature is high. place the bst capacitor and diode within 0.4 in. (10mm) of the bst pin. gate-drive resistors (r9 and r10) can often be useful to reduce jitter in the switching waveforms by slowing down the fast-slewing lx node and reducing ground bounce at the controller ic. low-valued resistors from around 1 to 5 are sufficient for many applications. c4 d2 v in = 5v v dd n1 r10 dh level translator control and drive logic n2 r9 pgnd r9 and r10 are optional lx dl bst max1624 max1625 figure 5. boost supply for gate drivers
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 16 ______________________________________________________________________________________ glitchcatcher current-boost driver (max1624) drivers for an optional current-boost circuit are includ - ed in the max1624 to improve transient response. some dynamically clocked cpus switch computational blocks on and off as needed to reduce power con - sumption, and can generate load steps of several amperes in a few tens of nanoseconds. the current- boost circuit is intended to improve transient response to such load steps by bypassing the inductor? lowpass filter operation. when the output drops out of regulation by more than 1.5% to 2.5%, the p-channel or n-channel switches turn on and force the output back into regulation. the mosfet drivers?response time is typically 75ns, and their minimum on-time is typically 100ns. current sense and overload current limiting the current-sense circuit resets the main pwm latch and turns off the high-side mosfet switch whenever the voltage difference between csh and csl from cur - rent through the sense resistor (r1) exceeds the peak current limit (100mv typical). current-mode control offers a practical level of over - load protection in response to many fault conditions. during normal operation, maximum output current is enforced by the peak current limit. if the output is short - ed directly to gnd through a low-resistance path, the current-sense comparator may be unable to enforce a current limit. under such conditions, circuit parasitics such as mosfet r ds(on) typically limit the short- circuit current to a value around the peak-current-limit setting. attach a lowpass-filter network between the current- sense pins and resistor to reduce high-frequency com - mon-mode noise (figure 6). the filter should be designed with a time constant of around 200ns. resistors in the 20 to 100 range are recommended for r7 and r8. connect the filter capacitors c11 and c12 from v cc to csh and csl, respectively. values of 39 and 4.7nf are suitable for many designs. place the current-sense filter network close to the ic, within 0.1 in. (2.5mm) of the csh and csl pins. internal soft-start soft-start allows a gradual increase of the internal cur - rent limit at start-up to reduce input surge currents. in the max1624/max1625, an internal dac raises the cur - rent-limit threshold from 0v to 100mv in four steps (25mv, 50mv, 75mv, and 100mv) over the span of 1536 oscillator cycles. __________________ design pr ocedur e setting the output voltage max1624 select the output voltage using the d0?4 pins. the max1624 uses an internal 5-bit dac as a feedback- resistor voltage divider. the output voltage can be digi - tally set in 100mv increments from 1.1v to 3.5v using the d0?4 inputs (table 4). d0?4 are logic inputs and accept both ttl and cmos voltage levels. the max1624 has both fb and agnd inputs, allowing a kelvin connection for remote voltage and ground sensing to eliminate the effects of trace resistance on the feedback voltage. (see pc board layout considerations for further details.) fb input current is 0.1 a (max). the max1624 dac codes were designed for compati - bility with intel specifications for output voltages between 3.5v and 2.1v. codes 10000 through 11110 are compatible with intel specifications, while codes 00000 through 01111 are not. codes 11111 and 01111 turn off the buck controller, placing the ic in a low- current mode (0.2ma typical). for compatibility with intel codes for output voltages below 2.1v, see the max1638/max1639 data sheet. c12 4.7nf r1 c11 4.7nf r7 39 w r6 100 w r8 39 w csh v cc csl max1624 max1625 n1 c9 0.1 m f c7 4.7 m f c1 v in figure 6. current-sense filter
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power ______________________________________________________________________________________ 17 max1625 set the output voltage by connecting r2 and r3 (fig- ure 7) to the fb pin from the output to agnd. r2 is given by the following equation: where v fb = 1.1v. since the input bias current at fb has a maximum value of 0.1 a, values up to 100k can be used for r3 with no significant accuracy loss. values under 1k are recommended to improve noise immunity and minimize parasitic capacitance at the fb node. place r2 and r3 very close to the max1625, within 0.2 in. (5mm) of the fb pin. selecting the oscillator frequency set the switching frequency between 100khz and 1mhz by connecting a resistor from freq to agnd. select the resistor according to the following equation: low-frequency operation reduces controller ic quies - cent current and improves efficiency. high-frequency operation reduces cost and pc board area by allowing the use of smaller inductors and fewer and smaller out - put capacitors. inductor energy-storage requirements and output capacitor requirements at 1mhz are one- third those at 300khz. choosing the error-amplifier gain (max1624) set the error-amplifier gain to match the voltage-preci - sion requirements of the cpu used. the max1624? loop-gain control input (lg) allows trade-offs in dc/ac voltage accuracy versus output filter capacitor require - ments. ac load regulation can be set to 0.5%, 1%, or 2% by connecting lg as shown in table 5. the max1625? default ac regulation is 1%. dc load regulation is typically 10 times better than ac load regulation, and is determined by the gain set by the lg pin. specifying the inductor three key inductor parameters must be specified: inductance value (l), peak current (i peak ), and dc resistance (r dc ). the following equation includes a constant lir, which is the ratio of inductor peak-to- peak ac current to dc load current. a higher lir value allows for smaller inductors and better transient response, but results in higher losses and output ripple. r x f osc 4 2 10 = 10 r r x v v out fb 2 3 1 = - ? ? ? ? ac load- regulation error (%) 1 lg connected to dc load- regulation error (%) ref 0.1 gnd 0.05 v cc 0.2 0.5 2 typical a e (v gain / i gain ) 8 2 4 table 4. output voltage-adjustment settings table 5. lg pin adjustment settings non-intel- compatible dac codes no cpu (off) 1 1 1 1 0 1.1 0 1 1 1 0 1.1 1 0 1.1 1 0 0 1 0 1.1 0 0 0 1 0 1.2 1 1 1 0 0 1.3 0 1 1 0 0 1.4 1 0 1 0 0 1.5 0 0 1 0 0 1.6 1 1 0 0 0 1.7 0 1 0 0 0 1.8 1 0 0 0 0 1.9 0 0 0 0 0 intel-compatible dac codes no cpu (off) 1 1 1 1 1 2.1 0 1 1 1 1 2.2 1 0 1 1 1 compatibility 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.5 3.1 3.3 3.2 3.4 output voltage (v) 0 1 1 0 0 1 1 0 0 0 1 1 0 d1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 d0 d2 d4 0 d3
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 18 ______________________________________________________________________________________ a good compromise between size and loss is a 45% ripple current to load current ratio (lir = 0.45), which corresponds to a peak inductor current 1.23 times higher than the dc load current. where f is the switching frequency, between 100khz and 1mhz; i out is the maximum dc load current; and lir is the ratio of ac to dc inductor current (typically 0.45). the exact inductor value is not critical and can be adjusted to make trade-offs among size, transient response, cost, and efficiency. although lower inductor values minimize size and cost, they also reduce efficien - cy due to higher peak currents. in general, higher inductor values increase efficiency, but at some point resistive losses due to extra turns of wire exceed the benefit gained from lower ac current levels. load- transient response can be adversely affected by high inductor values, especially at low (v in - v out ) differentials. the peak inductor current at full load is 1.23 x i out if the previous equation is used; otherwise, the peak cur - rent can be calculated using the following equation: the inductor? dc resistance is a key parameter for effi - cient performance, and should be less than the current- sense resistor value. calculating the current-sense resistor value calculate the current-sense resistor value according to the worst-case minimum current-limit threshold voltage (from the electrical characteristics ) and the peak inductor current required to service the maximum load. use i peak from the equation in the section specifying the inductor . the high inductance of standard wire-wound resistors can degrade performance. low-inductance resistors, such as surface-mount power metal-strip resistors, are preferred. the current-sense resistor? power rating should be higher than the following: in high-current applications, connect several resistors in parallel as necessary, to obtain the desired resis - tance and power rating. selecting the output filter capacitor output filter capacitor values are generally determined by effective series resistance (esr) and voltage-rating requirements, rather than by the actual capacitance value required for loop stability. due to the high switch - ing currents and demanding regulation requirements in a typical max1624/max1625 application, use only spe - cialized low-esr capacitors intended for switching- regulator applications, such as avx tps, sprague 595d, sanyo os-con, or nichicon pl series. do not use standard aluminum-electrolytic capacitors, which can cause high output ripple and instability due to high esr. the output voltage ripple is usually dominated by the filter capacitor? esr, and can be approximated as i ripple x r esr . to ensure stability, the capacitor must meet both minimum capacitance and maximum esr values as given in the following equations: c v v v v x r x f r r out ref out in min out sense osc esr sense ( ) > + ? ? ? ? < 1 r mv r power rating sense ( ) = 115 2 r mv i sense peak = 85 i i v v v f x l x v peak out out in max out osc in max ( ) ( ) = + - ( ) 2 l v v v v x f x i x lir out in max out in max osc out ( ) ( ) = - ( ) r3 place ver y close to max1625 r2 fb agnd v out load max1625 figure 7. max1625 adjustable output operation
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power ______________________________________________________________________________________ 19 compensating the feedback loop the feedback loop needs proper compensation to pre - vent excessive output ripple and poor efficiency caused by instability. compensation cancels unwanted poles and zeros in the dc-dc converter? transfer func - tion that are due to the power-switching and filter ele - ments with corresponding zeros and poles in the feedback network. these compensation zeros and poles are set by the compensation components cc1, cc2, and rc1. the objective of compensation is to ensure stability by ensuring that the dc-dc converter? phase shift is less than 180 by a safe margin, at the frequency where the loop gain falls below unity. one simple method for ensuring adequate phase mar - gin is to place pole-zero pairs to approximate a single- pole response with a -20db/decade slope all the way to unity-gain crossover (figure 8). (other compensation schemes are possible.) the order of undesired poles and zeros may differ from that shown in figure 8, depending on the characteristics of the load, output filter capacitor, switching frequency, and inductor. these procedures are guidelines only, and empirical experimentation is needed to select the compensation components?final values. canceling the sampling pole and output filter esr zero compensate the fast-voltage feedback loop by con - necting a resistor and a capacitor in series from the cc1 pin to agnd. the pole from cc1 can be set to cancel the zero from the filter-capacitor esr. thus the capacitor at cc1 should be as follows: resistor rc1 sets a zero that can be used to compen - sate for the sampling pole generated by the switching frequency. set rc1 to the following: the cc1 pin? output resistance is 10k . in the sam - pling pole equation (figure 8), d max is the maximum duty cycle, or v out / v in(min) . setting the dominant pole and canceling the load and output filter pole compensate the slow-voltage feedback loop by adding a ceramic capacitor from the cc2 pin to agnd. this is an integrator loop used to cancel out the dc load- regulation error. selection of capacitor cc2 sets the dominant pole and a compensation zero. the zero is typically used to cancel the unwanted pole generated by the load and output filter capacitor at the maximum load current. select cc2 to place the zero close to or slightly lower than the frequency of the unwanted pole, as follows: the transconductance of the integrator amplifier at cc2 is 1mmho. the voltage swing at cc2 is internally clamped around 2.4v to 3v minimum and 4v to v cc maximum to improve transient response times. cc2 can source and sink up to 100 a. cc mmho x c x v i out out out max 2 1 4 ( ) = rc v v f x cc out in osc 1 1 2 1 = + ? ? ? ? cc c x r k out esr 1 10 = w frequency (log) loop gain dominant pole from integra tor unw anted pole from r load c out compensa tion zero to cancel pole from r load c out compensa tion pole to cancel zero from c out r esr unw anted zero from c out r esr unw anted sampling pole compensa tion zero to cancel sampling pole desired response 2 p (rc1 x cc1) 2 p (10k w x cc1) 1 1 (1 + d max ) x p f osc(min) 2 p r esr x c out 1 2 p r load(max) x c out 1 2 p 50k w x cc2 1 1mmho 2 p x 4cc2 gain (db linear) figure 8. max1624/max1625 bode plot with compensation poles and zeros
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 20 ______________________________________________________________________________________ calculating the loop gain (optional) the loop gain is an important parameter in alternative compensation schemes: where a e is the error-comparator relative gain, and a i = 10 is the integrator gain. a e is 4 for the max1625, but it is 2, 4, or 8 for lg pin settings of v cc , ref, or agnd, respectively, for the max1624. feed-forward compensation (max1625) an optional compensation capacitor, typically 220pf, may be needed across the upper feedback resistor to counter the effects of stray capacitance on the fb pin, and to help ensure stable operation when high-value feedback resistors are used (figure 9). empirically adjust the feed-forward capacitor as needed. choosing the mosfet switches the two high-current n-channel mosfets must be logic-level types with guaranteed on-resistance specifi - cations at v gs = 4.5v. lower gate-threshold specs are better (i.e., 2v max rather than 3v max). gate charge should be less than 100nc to minimize switching losses and reduce power dissipation. i 2 r losses are the greatest heat contributor to mosfet power dissipation and are distributed between the high- and low-side mosfets according to duty factor, as follows: switching losses affect the upper mosfet only, and are insignificant at 5v input voltages. gate-charge losses are dissipated in the ic, and do not heat the mosfets. ensure that both mosfets are at a safe junction temper - ature by calculating the temperature rise according to package thermal-resistance specifications. the high-side mosfet? worst-case dissipation occurs at the maximum output voltage and minimum input voltage. for the low- side mosfet, the worst case is at the maximum input voltage when the output is short-circuited (consider the duty factor to be 100%). selecting the rectifier diode the rectifier diode d1 is a clamp that catches the nega - tive inductor swing during the 30ns typical dead time between turning off the high-side mosfet and turning on the low-side mosfet synchronous rectifier. d1 must be a schottky diode, to prevent the mosfet body diode from conducting. it is acceptable to omit d1 and let the body diode clamp the negative inductor swing, but efficiency will drop 1% or 2% as a result. use a 1n5819 diode for loads up to 3a, or a 1n5822 for loads up to 10a. adding the bst supply diode and capacitor a signal diode, such as a 1n4148, works well for d2 in most applications, although a low-leakage schottky diode provides slightly improved efficiency. do not use large power diodes, such as the 1n4001 or 1n5817. exercise caution in the selection of schottky diodes, since some types exhibit high reverse leakage at high operating tem - peratures. bypass bst to lx using a 0.1 f capacitor. selecting the input capacitors place a 0.1 f ceramic capacitor and 4.7 f capacitor between v cc and agnd, as well as between v dd and pgnd, within 0.2 in. (5mm) of the v cc and v dd pins. select low-esr input filter capacitors with a ripple- current rating exceeding the rms input ripple current, connecting several capacitors in parallel if necessary. rms input ripple current is determined by the input voltage and load current, with the worst-possible case occurring at v in = 2 x v out : i i v v v v i i when v v rms load max out in out in rms out in out ( ) / ( ) = - = = 2 2 p low side i x r x v v p low side shorted i x r where i mv r d load ds on out in d limit ds on limit sense ( ) ( , ) / . ( ) ( ) = - ? ? ? ? = = 2 1 115 2 p high side i x r x v v d load ds on out in ( ) ( ) = 2 loop gain db log a v v x r r x a log a v mv x e ref out load cs i e ref ( ) = ? ? ? ? = ? ? ? ? 20 20 85 10 r3 r2 optional feed- forw ard cap acitor fb agnd output max1625 figure 9. max1625 optional feed-forward compensation capacitors
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power ______________________________________________________________________________________ 21 bypassing the internal reference bypass the internal 3.5v reference at the ref pin by connecting a 0.1 f capacitor to agnd. use a larger value, such as 1 f, for high-current applications. choosing the glitchcatcher mosfets p-channel and n-channel switches and a series resistor are required for the current-boost circuit (figure 10). current through the mosfets and current-limiting resistors must be sufficient to supply the load current, with enough extra for prompt output regulation without excessive overshoot. design for boost-current values 1.5 times the maximum load current, and choose mosfets and current-limiting resistors such that: __________ applications infor mation efficiency considerations refer to the max796?ax799 data sheet for informa - tion on calculating losses and improving efficiency. pc board layout considerations good pc board layout and routing are required in high- current, high-frequency switching power supplies to achieve good regulation, high efficiency, and stability. the pc board layout artist must be provided with explicit instructions concerning the placement of power-switching components and high-current routing. it is strongly recommended that the evaluation kit pc board layouts be followed as closely as possible. contact maxim? applications department concerning the availability of pc board examples for higher-current circuits. in most applications, the circuit is on a multilayer board, and full use of the four or more copper layers is recommended. use the top layer for high-current power and ground connections. leave the extra cop - per on the board as a pseudo-ground plane. use the bottom layer for quiet connections (ref, fb, agnd), and the inner layers for an uninterrupted ground plane. a ground plane and pseudo-ground plane are essential for reducing ground bounce and switching noise. follow these steps: 1) place the high-power components (c1, r1, n1, d1, n2, l1, and c2 in figure 1) as close together as possible, following these priorities: minimize ground-trace lengths in high-current paths. the surface-mount power components should be butted up to one another with their ground terminals almost touching. connect their ground terminals using a wide, filled zone of top- layer copper (the pseudo-ground plane), rather than through the internal ground plane. at the out - put terminal, use vias to connect the top-layer pseudo-ground plane to the normal inner-layer ground plane at the output filter capacitor ground terminals. this minimizes interference from ir drops and ground noise, and ensures that the ic? agnd is sensing at the supply? output terminals. r r v v i and r r v i dson p max limit in out out max dson n max limit out out max , ( ) ( ) , ( ) ( ) . . + ? - + ? 1 5 1 5 r11 input 5v c3 c2 c1 output 1.1v to 3.5v n3 ndrv pdrv load max1624 p1 figure 10. glitchcatcher circuit
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 22 ______________________________________________________________________________________ minimize high-current path trace lengths. use very short and wide traces. from c1 to n1: 0.4 in. (10mm) max length; d1 cathode to n2: 0.2 in. (5mm) max length; lx node (n1 source, n2 drain, d1 cathode, inductor l1): 0.6 in. (15mm) max length. 2) place the max1624/max1625 and supporting components following these rules: minimize trace lengths to the current-sense resistor. the ic must be no farther than 0.4 in. (10mm) from the current-sense resistor. use a kelvin connection. minimize ground trace lengths between the max1624/max1625 and supporting compo - nents. connect components for the ref, cc1, cc2, and freq pin directly to agnd. connect agnd and pgnd at the ic. keep noisy nodes and components away from sensitive analog nodes, such as the current- sense, voltage-feedback, ref, cc1, cc2, and freq pins. placing the ic and analog compo - nents on the opposite side of the board from the power-switching node is desirable. noisy nodes include the main switching node (lx), inductor, and gate-drive outputs. place components for the freq, ref, cc1, and cc2 pins as close to the ic as possible, within 0.2 in. (5mm). keep the gate-drive traces (dh, dl, and bst) shorter than 20mm, and route them away from csh, csl, ref, fb, etc. filter the v cc supply input to the ic. bypass the ic directly from v dd to pgnd using a 0.1 f ceramic capacitor and 4.7 f electrolytic capacitor placed within 0.2 in. (5mm) of the ic. place the voltage-feedback components close to the fb pin of the max1625, within 0.2 in. (5mm). connect the voltage-feedback trace directly to the cpu? power input and route it to avoid noisy traces.
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power ______________________________________________________________________________________ 23 ___________________ chip infor mation transistor count: 2472 substrate connected to agnd 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 dh lx pgnd dl csh csl pwrok bst top view v dd pdrv ndrv d3 lg d0 d1 d2 16 15 14 13 9 10 11 12 d4 freq cc2 cc1 fb agnd ref v cc ssop max1624 __________________________________________________________ pin configurations 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 bst dh lx pgnd dl v dd freq cc2 cc1 max1625 so pwrok csl ref csh v cc agnd fb
max1624/max1625 high-speed step-down contr ollers with synchr onous rectification for cpu power 24 ______________________________________________________________________________________ ________________________________________________________ package infor mation ssop.eps

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